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asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 1 - general description the ak4702 offers the ideal features for digital set- top-box systems. using akm's multi-bit architecture for its modulator, the ak4702 delivers a wide dynamic range while preserving linearity for improved thd+n performance. the ak4702 integrates a combi nation of scf and ctf filters, removing the need for high cost external filters and increasing performance for systems with excessive clock jitter. the ak4702 also including the audio switches and volumes designed primarily for digital set-top-box systems. the ak4702 is offered in a space saving 48-pin lqfp package. features dac ? sampling rates ranging from 8khz to 50khz ? 18bit 8x fir digital filter ? 2nd order analog lpf ? on chip buffer with single-ended output ? digital de-emphasis for 32k, 44.1k and 48khz sampling ? i/f format: 18bit msb justified, 18/16bit lsb justified, i 2 s ? master clock: 256fs, 384fs ? high tolerance to clock jitter analog switches for scart audio section ? thd+n: -86db (@2vrms) ? dynamic range: 96db (@2vrms) ? stereo analog volume with zero-cross detection circuit (+6db to ?60db & mute) ? five analog inputs two stereo input (tv, vcr scart) one mono input for tone ? five analog outputs two stereo outputs (tv, vcr scart) one mono output ? loop-through mode for standby ? pop noise free circuit for power on/off video section ? 75ohm driver ? 6db gain for outputs ? adjustable gain ? four cvbs/y inputs (encx2, tv, vcr), three cvbs/y output (rf, tv, vcr) ? three r/c inputs (encx2, vcr), two r/c output (tv, vcr) ? bi-directional control for vcr-chroma/red ? two g and b inputs (enc, vcr), one g and b outputs (tv) power supply ? 5v+/-5% and 12.6v~10v ? low power dissipation package ? small 48pin lqfp 2ch dac with av scart switch a k4702eq
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 2 - tvoutl monoout tvoutr vcroutl vcroutr monoin +6 to -60db (2db/step) -6db/0db/2.44db tvinl tvinr vcrinl vcrinr dac mclk bick lrck sdata bias (mute) vol um e #0 vol um e #1 sck sda register control pdn vcom5 vcom12 vd vp vss vcr1/0 tv1/0 vol mono audio block
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 3 - enc c tvrc enc g/cvbs vcr g tvg enc b vcr b tvb enc y tvvout rfv 6db 6db 6db 6db 0, 1, 2, 3db enc r/c vcrvout vcrc 6db 6db vcr cvbs/y tv cvbs vcr r/c enc cvbs/y encc encg vcrg encb vcrb enc y encrc vcrvin tvvin vcrrc enc v ( typical connection ) rf mod tv scart vcr scart ( typical connection ) vvd2 vvss vvd1 6db video block monitor vcr fb tvfb 6db 0v 2v tvsb vcrsb 0/ 6/ 12v 0/ 6/ 12v vcrfb ( typical connection ) tv scart vcr scart ( typical connection ) int video blanking block
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 4 - ? ordering guide AK4702EQ -10 +70 c 48pin lqfp (0.5mm pitch) ? pin layout vcrc tvfb 1 vvd1 48 2 vvss 3 tvvout 4 vvd2 5 tvrc 6 7 tvg 8 tvb 9 encb 10 encg 11 vcrvout 47 rfv 46 pdn 45 sda 44 scl 43 lrck 42 sdti 41 bick 40 mclk 39 vd 38 encv 13 ency 14 tvvin 15 vcrvin 16 vcrfb 17 vcrrc 18 vcrg 19 vcrb 20 int 21 vcrsb 22 tvsb 23 35 34 33 32 31 30 29 28 27 26 25 dvcom vp vcroutl vcroutr monoin tvinl monoout tvoutl tvoutr tvinr vcrinl AK4702EQ top view encrc 12 vcrinr 24 36 pvcom vss 37 encc ? compatibility with ak4702 ak4702 AK4702EQ thd+n at 3vrms output -60db - dg, dp -/+3%, -/+3deg (min/max) 0.4%, 0.8deg (typ)
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 5 - pin/function no. pin name i/o function 1 vcrc o chrominance output pin for vcr 2 vvss - video ground pin. 0v. 3 tvvout o composite/luminance output pin for tv 4 vvd2 - video power supply pin #2. 5v normally connected to vvss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 5 tvrc o red/chrominance output pin for tv 6 tvg o green output pin for tv 7 tvb o blue output pin for tv 8 vvd1 - video power supply pin #1. 5v normally connected to vvss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 9 encb i blue input pin for encoder 10 encg i green input pin for encoder 11 encrc i red/chrominance input pin1 for encoder 12 encc i chrominance input pin2 for encoder 13 encv i composite/luminance input pin1 for encoder 14 ency i composite/luminance input pin2 for encoder 15 tvvin i composite/luminance input pin for tv 16 vcrvin i composite/luminance input pin for vcr 17 vcrfb i fast blanking input pin for vcr 18 vcrrc i red/chrominance input pin for vcr 19 vcrg i green input pin for vcr 20 vcrb i blue input pin for vcr 21 int o interrupt pin for video blanking 22 vcrsb i/o slow blanking input/output pin for vcr 23 tvsb o slow blanking output pin for tv 24 vcrinr i rch vcr audio input pin 25 vcrinl i lch vcr audio input pin 26 tvinr i rch tv audio input pin 27 tvinl i lch tv audio input pin 28 monoin i mono input pin 29 vcroutr o rch analog output pin1 30 vcroutl o lch analog output pin1 31 tvoutr o rch analog output pin2 32 tvoutl o lch analog output pin2 33 monoout o mono analog output pin 34 vp - power supply pin. 12v normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 35 dvcom o dac common voltage pin normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 36 pvcom o audio common voltage pin normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. the caps affect the settling time of audio bias level.
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 6 - pin/function (continued) 37 vss - ground pin. 0v. 38 vd - dac power supply pin. 5v normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 39 mclk i master clock input pin an external ttl clock should be input on this pin. 40 bick i audio serial data clock pin 41 sdti i audio serial data input pin 42 lrck i l/r clock pin 43 scl i control data clock pin 44 sda i/o control data pin 45 pdn i power-down mode pin when at ?l?, the ak4702 is in the power-down mode and is held in reset. the ak4702 should always be reset upon power-up. 46 rfv o composite output pin for rf modulator 47 vcrvout o composite/luminance output pin for vcr 48 tvfb o fast blanking output pin for tv note: all input pins except pull-up/down pin should not be left floating.
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 7 - internal equivalent circuits pin no. pin name type equivalent circuit description 39 40 41 42 43 45 mclk bick sdti lrck scl pdn digital in vd 200 vss 44 sda digital i/o vd vss 200 i2c bus voltage must not exceed vd. 21 int digital out vss normally connected to vd(5v) through 10kohm resister externally. 46 47 48 1 3 5 6 7 rfv vcrout tvfb vcrc tvvout tvrc tvg tvb video out vvd1 vvss vvd2 vvss
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 8 - pin no. pin name type equivalent circuit description 9 10 11 12 13 14 15 16 17 18 19 20 encb encg encrc encc encv ency tvvin vcrvin vcrfb vcrrc vcrg vcrb video in vvd1 200 vvss 22 23 vcrsb tvsb video sb vp vss vp vss vss 200 (120k) the 120kohm is not attached for tvsb. 24 25 26 27 28 vcrinr vcrinl tvinr tvinl monoin audio in vp 200 vss 29 30 31 32 33 vcroutr vcroutl tvoutr tvoutl monoou t audio out vp vss vp vss 100 35 36 dvcom pvcom vcom out vd vss vd vss 100 vd vss
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 9 - absolute maximum ratings (vss=vvss=0v;note: 1) parameter symbol min max units power supply vd vvd1 vvd2 vp |vss-vvss| (note: 2) -0.3 -0.3 -0.3 -0.3 - 6.0 6.0 6.0 14 0.3 v v v v v input current (any pins except for supplies) iin - 10 ma input voltage vind -0.3 vd+0.3 v video input voltage vinv -0.3 vvd1+0.3 v audio input voltage vina -0.3 vp+0.3 v ambient operating temperature ta -10 70 c storage temperature tstg -65 150 c note: 1. all voltages with respect to ground. note: 2. vss and vvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss=vvss=0v; note: 1) parameter symbol min typ max units power supply vd vvd1 vvd2 vp 4.75 4.75 vvd1 10 5.0 5.0 5.0 12 5.25 vvd2 5.25 12.6 v v v v note: 3. analog output voltage scales with the voltage of vd. aout (typ@0db) = 2vrms vd/5. *akm assumes no responsibility for the usage beyond the conditions in this datasheet. electrical characteristics (ta = 25 c; vp=12v, vd = 5v; vvd1=vvd2 = 5v; fs = 48khz; bick = 64fs) power supplies power supply current normal operation (pdn = ?h?; note: 4) vd vvd1+vvd2 vp power-down mode (pdn = ?l?; note: 5) vd vvd1+vvd2 vp 14 20 5 10 10 10 30 40 10 100 100 100 ma ma ma a a a note: 4. stby bit ="l", all video outputs active. no signal, no load for a/v switches. fs=48khz ?0?data input for dac. note: 5. all digital inputs including clock pins (mclk, bick and lrck) are held at vd or vss.
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 10 - digital characteristics (ta = 25 c; vd = 4.75 5.25v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.0 - - - - 0.8 v v low-level output voltage (sda pin : iout= 3ma, int pin : iout= 1ma) vol - - 0.4 v input leakage current iin - - 10 a analog characteristics (audio) (ta = 25 c; vp=12v, vd = 5v; vvd1=vvd2 = 5v; fs = 48khz; bick = 64fs; signal frequency = 1khz; 18bit input data; measurement frequency = 20hz 20khz; r l 4.5k ? ; volume#0=volume#1=0db, 0db=2vrms output; unless otherwise specified) parameter min typ max units dac resolution 18 bit stereo input: (tvinl/tvinr/vcrinl/vcrinr pins) analog input characteristics input voltage 2 vrms input resistance 100 150 - k ? mono input: (monoin pin) analog input characteristics input voltage 1 vrms input resistance 40 60 - k ? stereo/mono output: (tvoutl/tvoutr/vcroutl/vcroutr/monoout pins; note: 6) analog output characteristics volume#0 step width (0db to ?6db) 6 db volume#1 step width (+6db to ?12db) (-12db to ?40db) (-40db to ?60db) 1.6 0.5 0.1 2 2 2 2.4 3.5 3.9 db db db thd+n (at 2vrms output. note: 7) -86 -80 db dynamic range (-60db output, a-weighted. note: 7) 92 96 db s/n (a-weighted. note: 7) 92 96 db interchannel isolation (note: 7, note: 8) 80 90 db interchannel gain mismatch (note: 7, note: 8) - 0.3 - db gain drift - 200 - ppm/ c load resistance (ac-lord; note: 9) tvoutl/r, vcroutl/r, monoout 4.5 k ? output voltage (note: 9, note: 10) 1.85 2 2.15 vrms power supply rejection (psr. note: 11) - 50 db note: 6. measured by audio precision system two cascade. note: 7. dac to tvout. note: 8. between tvoutl and tvoutr with digital inputs 1khz/0dbfs. note: 9. thd+n : -80db(min. at 2vrns). note: 10. full-scale output voltage by dac (0dbfs). output voltage of dac scales with the voltage of vd, stereo output (typ@0dbfs) = 2vrms vd/5 when volume#0=volume#1=0db. do not output signals over 3vrms. note: 11. the psr is applied to vd with 1khz, 100mv.
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 11 - filter characteristics (audio) (ta = 25 c; vp=10.0 12.6v, vd = 4.75 5.25v, vvd1=vvd2 = 4.75 5.25v; fs = 48khz; dem0 = ?1?, dem1 = ?0?) parameter symbol min typ max units digital filter passband 0.05db (note: 12) -6.0db pb 0 - 24.0 21.77 - khz khz stopband (note: 12) sb 26.23 khz passband ripple pr 0.06 db stopband attenuation sa 54 db group delay (note: 13) gd - 19.1 - 1/fs digital filter + lpf frequency response 0 20.0khz fr - 0.5 - db note: 12. the passband and stopband frequencies scale with fs (system sampling rate). ex.) pb=0.4535fs (@ 0.05db), sb=0.546fs. note: 13. the calculating delay time which occurred by digital filtering. this time is from setting the 16/18bit data of both channels to input register to the output of analog signal. analog characteristics (video) (ta = 25 c; vp=12v, vd = 5v; vvd1=vvd2 = 5v; vvol1/0= ?00? unless specified.) parameter conditions min typ max units sync tip clamp voltage at output 0.7 v chrominance bias voltage at output 2.2 v gain input=0.3vp-p, 100khz 5.5 6 6.5 db vvol1/0= ?00? 5.5 6 6.5 db vvol1/0= ?01? 6.7 7.2 7.7 db vvol1/0= ?10? 7.7 8.2 8.7 db rgb gain input=0.3vp-p, 100khz vvol1/0= ?11? 8.6 9.1 9.6 db interchannel gain mismatch input=0.3vp-p, 100khz (note: 14) -0.3 - 0.3 db frequency response input=0.3vp-p, response at 6mhz -1 -0.5 db input impedance chrominance input (internally biased) 40 60 - kohm input signal f=100khz, maximum with distortion < 1.0%, gain=6db. - - 1.5 vpp load resistance except rfv pin (note: 15) rfv pin (note: 16) 150 20k - - - - ohm ohm load capacitance c1 (note: 15) c2 (note: 15, note: 16) 400 15 pf pf dynamic output signal f=100khz, maximum with distortion < 1.0% - - 3 vpp y/c cross talk f=4.43mhz, 1vp-p input. among tvvout, tvrc, vcrvout and vcrc outputs. - -50 - db s/n reference level = 0.7vp-p, ccir 567 weighting. bw= 15khz to 5mhz. - 74 - db differential gain 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. - +0.4 - % differential phase 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. - +0.8 - degree
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 12 - note: 14. tvrc, tvg, tvb. note: 15. refer the figure 1. video signal output 75 ohm 75 oh m max: 400pf c1 r1 r2 max: 15pf c2 figure 1. load resistance r1+r2, and load capacitance c1 and c2. note: 16. ac load. refer the figure 2. video signal output 20k ohm (ac load) max: 15pf c2 r1 figure 2. load resistance r1 and load capacitance c1 switching characteristics (ta = 25 c; vp=10.0 12.6v, vd = 4.75 5.25v, vvd1=vvd2 = 4.75 5.25v; c l = 20pf) parameter symbol min typ max units master clock frequency 256fs: duty cycle 384fs: duty cycle fclk dclk fclk dclk 2.048 40 3.072 40 12.8 60 19.2 60 mhz % mhz % lrck frequency duty cycle fs duty 8 45 50 55 khz % audio interface timing bick period bick pulse width low pulse width high bick ? ? to lrck edge (note: 17) lrck edge to bick ? ? (note: 17) sdti hold time sdti setup time tbck tbckl tbckh tblr tlrb tsdh tsds 312.5 100 100 50 50 50 50 ns ns ns ns ns ns ns control interface timing (i 2 c bus): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling (note: 18) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp - 4.7 4.0 4.7 4.0 4.7 0 0.25 - - 4.0 0 100 - - - - - - - 1.0 0.3 - 50 khz s s s s s s s s s s ns reset timing pdn pulse width (note: 19) tpd 150 ns
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 13 - note: 17. bick rising edge must not occur at the same time as lrck edge. note: 18. data must be held for sufficient time to bridge the 300 ns transition time of scl. note: 19. the ak4702 should be reset by pdn= ?l? upon power up. note: 20. i 2 c is a registered trademark of philips semiconductors.
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 14 - ? timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr serial interface timing
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 15 - tpd vil pdn power-down timing thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 16 - operation overview ? system clock the external clocks required to operate the dac section of ak4702 are mclk, lrck and bick. the master clock (mclk) corresponds to 256fs or 384fs. mclk frequency is automatically detected, and the internal master clock becomes 256fs. the mclk should be synchronized with lrck but the phase is not critical. table 1 illustrates corresponding clock frequencies. all external clocks (mclk, bick and lrck) should always be present whenever the dac section of ak4702 is in the normal operating mode (stby bit = ?0?). if these clocks are not provided, the ak4702 may draw excess current because the device utilizes dynamically refreshed logic internally. the dac section of ak4702 should be reset by stby = ?0? after threse clocks are provide d. if the external clocks are not present, place the ak4702 in power-down mode (stby bit = ?1?). after exiting reset at power-up etc., the ak4702 remains in power-down mode until mclk and lrck are input. lrck mclk bick fs 256fs 384fs 64fs 32.0khz 8.1920mhz 12.2880mhz 2.0480mhz 44.1khz 11.2896mhz 16.9344mhz 2.8224mhz 48.0khz 12.2880mhz 18.4320mhz 3.0720mhz table 1. system clock example ? audio serial interface format data is shifted in via the sdti pin using bick and lrck inputs. the dif0 and dif1 bits can select four formats in serial mode as shown in table 2. in all modes, the serial data is msb-first, 2?s compliment format and is latched on the rising edge of bick. mode 2 can also be used for 16 msb justified formats by zeroing the unused two lsbs. mode dif1 dif0 sdti format bick figure 0 0 0 16bit lsb justified 32fs figure 3 1 0 1 18bit lsb justified 36fs figure 3 2 1 0 18bit msb justified 36fs figure 4 3 1 1 18bit i 2 s compatible 36fs or 32fs figure 5 default table 2. audio data formats sdti lrck bick 14 0 14 0 mode 0 don?t care don?t care 15:msb, 0:lsb sdti mode 1 17:msb, 0:lsb 15 14 0 15 14 0 don?t care don?t care 17 16 17 16 lch data rch data 15 15 figure 3. mode 0,1 timing
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 17 - lrck bick sdti 17:msb, 0:lsb 16 1 0 don?t care 17 lch data rch data 16 1 0don?t care 17 16 17 figure 4. mode 2 timing lrck bick sdti 17:msb, 0:lsb 16 1 0 don?t care 17 lch data rch data 16 1 0 don?t care 17 17 figure 5. mode 3 timing ? de-emphasis filter a digital de-emphasis filter is available for 32, 44.1 or 48khz sampling rates (tc = 50/15s) and is controlled by the dem0 and dem1 bits. dem1 dem0 mode 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 3. de-emphasis filter control
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 18 - ? volume/switch control the ak4702 has analog volume controls and switch matrix es designed primarily for scart routing. those are controlled via the control register as shown in, table 4, table 5, table 7 and table 8. (please refer to the block diagram in figure 1.) dvol1 dvol0 gain output level (at volume#1=0db) 0 0 0db 2vrms 0 1 -6db 1vrms 1 0 2.44db 2.65vrms 1 1 (reserved) (reserved) table 4. volume #0 (digital volume for dac) l5 l4 l3 l2 l1 l0 gain 1 0 0 0 1 0 +6db 1 0 0 0 0 1 +4db 1 0 0 0 0 0 +2db 0 1 1 1 1 1 0db (default) ? ? ? ? ? ? ? 0 0 0 0 0 1 -60db 0 0 0 0 0 0 mute note: do not exceed 3vrms as analog output. table 5. volume #1 (analog volume) tv1 tv0 source of tvoutl/r 0 0 dac 0 1 vcrin (default) 1 0 mute 1 1 (reserved) table 6. tvout switch configuration vol tv1 tv0 source of monoout 0 0 0 dac (l+r)/2 0 0 1 dac (l+r)/2 0 1 0 dac (l+r)/2 bypass the volume #1 0 1 1 (reserved) 1 0 0 dac (l+r)/2 1 0 1 vcrin (l+r)/2 through the volume #1 1 1 0 mute 1 1 1 (reserved) table 7. monoout switch configuration vcr1 vcr0 source of vcroutl/r 0 0 dac 0 1 tvin (default) 1 0 mute 1 1 (reserved) table 8. vcrout switch configuration
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 19 - ? zero-cross detection and offset calibration to minimize the click noise when changing the gain of volume#1, the ak4702 has a zero-cross detection and an offset calibration function. 1. zero-cross detection function when the zero bit = ?1?, the zero-cross detection function is enabled. the gain of volume#1 changes at the first zero-cross point from the acknowledgement of a volume changing command or when the zero-cross is not detected within the time set by ztm1-0 bits (256/fs to 2048/fs). the zero-cross counter is initialized whenever a gain is issued. the zero-cross is detected on l/r channels independently. to disable this function, set the zero bit to ?0?. zero: zero-cross detection enable for volume#1 0 : disable. the volume value changes immediately without zero-cross. 1 : enable (default). the volume value changes at a zero-crossing point or when timeout (ztm1-0 bit setting) occurs. the internal comparator for zero-cross detection has a small offset. therefore, the gain of volume #1 may change due to a zero-cross timeout before the comparator-based zero-cross detection occurs. when the new gain value 1eh(-2db) is written while the gain of both lch and rch are 1fh(0db), if the lch detects the zero-cross prior to rch, only the gain of lch changes to 1eh(- 2db) while rch waits for a zero-cross. after that, if the gain is set to 1dh(-4db) before either a zero-cross or zero-cross timeout, the rch keeps the same value and changes from 1fh to 1dh at next zero-cross or timeout. 1fh lch gain rch gain gain registers zero-cross 1fh 1eh 1dh 1dh 1eh 1fh 1dh wr[gain=1eh] wr[gain=1dh] zero-cross timer initialized timeout; (may have click noise) timer (256/fs to2048/fs) figure 6. zero-cross operation (zero= ?1?) 2. offset calibration function offset calibration is enabled when the cal bit = ?1?. this function begins when the tvout source is switched to dac after the stby bit is changed to ?0?. it takes 1664/fs to execute the offset calibration cycle. during the offset calibration cycle, the analog outputs are muted. once the offset calibration is executed, the calibration memory is held until pdn= ?l? or the new calibration is executed. when the switch is changed from dac to vcr during calibration, the calibration is discontinued, and resumed when tvout is switched back to dac. if volume#1 gain is changed during calibration, the change takes place after calibration is complete. ? standby mode when the mute bit = ?0? and the stby bit = ?1?, the ak4702 is forced into tv-vcr loop through mode. in this mode, the sources of tvoutl/r and monoout are fixed to vcrinl/r, the sources of vcroutl/r are fixed to tvinl/r respectively. the gain of volume#1 is fixed to 0db. since all registers are not initialized by stby= ?1?, a register switch configuration requires standby mode (stby= ?0?).
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 20 - ? system reset and power-down control the ak4702 should be reset once by bringing pdn = ?l? upon power-up. the ak4702 has several power-down modes. the pdn pin, mute bit and stby bit control them as shown in table 9 and table 10. pdn pin: power down pin. ?h?: normal operation ?l?: device power down. mute bit: analog mute bit. ?1?: mute all analog outputs ?0?: normal operation stby bit : standby bit. ?1?: standby mode, dac is powered down, volume is fixed to 0db, the analog audio/video paths are fixed to tv-vcr loop-through. ?0?: normal operation. after when the pdn pin is set to ?h?, the ak4702 is in standby mode and muted. to exit the mute and enter standby mode, set the mute bit to ?0? and the stby bit to ?1?. to use the dac or change analog switches, set the stby bit to ?0?. the dac will power up and the internal timing starts clocking lrck ? ? after exiting reset and power down states by mclk. the ak4702 is in power-down mode until mclk and lrck are input. mode pdn pin mute bit stby bit mclk, bick, lrck dac analog outputs register control 0 device power-down ?l? * * not needed powered down gnd not available 1 standby and mute (default) ?h? 1 1 not needed powered down gnd available 2 standby ?h? 0 1 not needed powered down fixed to tv-vcr loop-through available 3 mute ?h? 1 0 needed active gnd available 4 normal operation ?h? 0 0 needed active active available table 9. power-down modes (audio) mode pdn pin stby bit video outputs tvfb, tvsb vcrsb 0 power-down ?l? * hi-z hi-z internally pulled down by 120kohm(typ) resister 1 standby ?h? 1 active (path is fixed) active active 2 normal operation ?h? 0 active active active table 10. power-down modes (video)
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 21 - the figure 7 shows an example of the system timing at the power-down and power-up by pdn pin. pdn p in gd d/a out (internal) (1) tv out ?1? (default) stby bit ?0? ?1? don?t care (2) clock in normal operation don?t care (2) don?t care data in don?t care ?0? gd (1) ?0? dac tv-source select vcr in vcr in ?1? (default) mute bit ?0? ?stand-by? vcr in (3) vcr in fixed to vcr in(loop-through) ?1? ?0? ?stand-by? ?mute? audio data ?1? (default) offset calibration (4) notes: (1) the analog output corresponding to the digital input has a group delay, gd. (2) the external clocks (mclk, bick and lrck) can be stopped in standby mode. (3) please mute the analog outputs externally if click noise(3) adversely affects the system. (4) in case of the cal bit = ?1?, the offset calibration is always executed when the source of tvout is switched to dac after the stby bit is changed to ?0?. to disable this function, set the cal bit = ?0?. figure 7. power-down/up sequence example
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 22 - ? mode control interface i 2 c-bus control mode the ak4702 supports the standard-mode i 2 c-bus (max: 100khz). then ak4702 doesn?t support the fast-mode i 2 c-bus system (max: 400khz). 1. write operations figure 8 shows the data transfer sequence in i 2 c-bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition (figure 14). after the start condition, a slave address is sent. this address is 7 bits long followed by an eighth bit which is a data direction bit (r/w). the most significant seven bits of the slave address are fixed as ?0010001?. if the slave address match that of the ak4702, the ak4702 generates the acknowledge and the operation is executed. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse (figure 15). a ?1? for r/w bit indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. the second byte consists of the address for control registers of the ak4702. the format is msb first, and those most significant 3-bits are fixed to zeros (figure 10). the data after the second byte contain control data. the format is msb first, 8bits (figure 11). the ak4702 generates an acknowledge after each byte has been received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition (figure 14). the ak4702 can execute multiple one byte write operations in a sequence. after receipt of the third byte, the ak4702 generates an acknowledge, and awaits the next data again. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. if the address exceeds 08h prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low (figure 16) except for the start and the stop condition. sda s t a r t a c k a c k s slave a ddress a c k sub a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= ?0? a c k figure 8. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 0 1 r/w figure 9. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 10. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 11. byte structure after the second byte
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 23 - 2. read operations set r/w bit = ?1? for read operations. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of terminating the write cycle after the receipt the first data word. after the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. if the address exceeds 08h prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the ak4702 supports two basic read operations: current address read and random read. 2-1. current address read the ak4702 contains an internal address counter that maintain s the address of the last word accessed, incremented by one. therefore, if the last access (either a read or writ e) was to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit set to ?1?, the ak4702 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but generate the stop condition, the ak4702 discontinues transmission sda s t a r t a c k a c k s slave a ddress a c k data(n+1) p s t o p data(n+x) a c k data(n+2) a c k r/w= ?1? a c k data(n) figure 12. current address read 2-2. random read random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues a start condition, slave address(r/w=?0?) and then the register address to read. after the register?s address is acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to ?1?. then the ak4702 generates an acknowledge, 1-byte data and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but generate the stop condition, the ak4702 discontinues transmission. sda s t a r t a c k a c k s slave a ddress a c k data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= ?0? a c k sub a ddress(n) s t a r t a c k s slave a ddress r/w= ?1? figure 13. random address read
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 24 - scl sda stop condition start condition s p figure 14. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 15. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 16. bit transfer on the i 2 c-bus
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 25 - ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control dem1 dem0 dif1 dif0 0 0 mute stby 01h switch vmute mmon vcr1 vcr0 mono vol tv1 tv0 02h main volume 0 0 l5 l4 l3 l2 l1 l0 03h zerocross 0 0 cal dvol1 dvol0 zero ztm1 ztm0 04h video switch vrf1 vrf0 vvcr2 vvcr1 vvcr0 vtv2 vtv1 vtv0 05h video output enable cio tvfb vcrc vcrv tvb tvg tvr tvv 06h video volume/clamp 0 vclp1 vclp0 0 clamp1 clamp0 vvol1 vvol0 07h s/f blanking control sbio1 sbio0 sbv1 sbv0 sbt1 sbt0 fb1 fb0 08h s/f blanking monitor 0 0 0 0 0 fvcr svcr1 svcr0 when the pdn pin goes ?l?, the registers are initialized to their default values. while the pdn=?h?, all registers can be accessed. do not write any data to the register over 08h. ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control dem1 dem0 dif1 dif0 0 0 mute stby r/w r/w default 0 1 1 1 0 0 1 1 stby: standby control 0 : normal operation 1 : standby mode(default). all registers are not initialized. dac : powered down and timings are reset. gain of volume#1 : fixed to 0db, source of tvout : fixed to vcrin, source of vcrout : fixed to tvin, source of monoout : fixed to vcrin, source of tvvout : fixed to vcrvin(or hi-z), source of tvrc : fixed to vcrrc(or hi-z), source of tvg : fixed to vcrg(or hi-z), source of tvb : fixed to vcrb(or hi-z), source of vcrvout : fixed to tvvin(or hi-z), source of vcrc : fixed to hi-z or vss(controlled by cio bit). mute: audio output control 0 : normal operation 1 : all audio outputs to gnd (default) dif1-0: audio data interface format control 00 : 16bit lsb justified 01 : 18bit lsb justified 10 : 18bit msb justified 11 : 18bit i 2 s compatible (default) dem1-0: de-emphasis response control 00 : 44.1khz 01 : off (default) 10 : 48khz 11 : 32khz
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 26 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h switch vmute mmon vcr1 vcr0 mono vol tv1 tv0 r/w r/w default 1 1 0 1 0 1 0 1 tv1-0: tvout source switch 00 : dac 01 : vcrin (default) 10 : mute 11 : (reserved) vol: source select for monoout 0 : bypass the volume (fixed to dac out) 1 : through the volume (default) mono: mono select for tvout 0 : stereo. (default) 1 : mono. (l+r)/2 vcr1-0: vcrout source switch 00 : dac 01 : tvin (default) 10 : mute 11 : (reserved) mmon: mute of monoin input 0 : add the monoin 1 : mute the monoin (default) vmute: mute switch for volume#1 0 : normal operation 1 : mute the volume#1 (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h main volume 0 0 l5 l4 l3 l2 l1 l0 r/w r/w default 0 0 0 1 1 1 1 1 l5-0: volume#1 control those registers control both lch and rch of volume#1. 111111 to 100011 : (reserved) 100010 : volume gain = +6db 100001 : volume gain = +4db 100000 : volume gain = +2db 011111 : volume gain = +0db (default) 011110 : volume gain = -2db ... 000011 : volume gain = -56db 000010 : volume gain = -58db 000001 : volume gain = -60db 000000 : volume gain = mute
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 27 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h zerocross 0 0 cal dvol1 dvol0 zero ztm1 ztm0 r/w r/w default 0 0 1 0 0 1 1 1 ztm1-0: the time length control of zero-cross timeout 00 : typ. 256/fs 01 : 512/fs 10 : 1024/fs 11 : 2048/fs (default) zero: zero-cross detection enable for volume control#1 0 : disable the volume value changes immediately without zero-cross. 1 : enable (default) the volume value changes when timeout or zero-cross before timeout. this function is disabled when stby= ?1?. dvol1-0: digital volume control for dac (volume#0) 00 : 0db 01 : -6db 10 : +2.44db 11 : (reserved) cal: offset calibration enable 0 : offset calibration disable. 1 : offset calibration enable(default)
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 28 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h video switch vrf1 vrf0 vvcr2 vvcr1 vvcr0 vtv2 vtv1 vtv0 r/w r/w default 1 0 0 1 1 1 0 0 vtv0-2: selector for tv video output mode vtv2-0 tvvout tvrc tvg tvb shutdown 000 hi-z hi-z hi-z hi-z encoder cvbs or rgb 001 encoder cvbs encv encoder r encrc encoder g encg encoder b encb encoder y/c 1 010 encoder luminance encv encoder chrominance encrc hi-z hi-z encoder y/c 2 011 encoder luminance ency encoder chrominance encc hi-z hi-z vcr (default) 100 vcr cvbs/y vcrvin vcr r/c vcrrc vcr g vcrg vcr b vcrb tv cvbs 101 tv cvbs/y tvvin hi-z hi-z hi-z (reserved) 110 - - - - (reserved) 111 - - - - table 11. tv video output (see note) vvcr0-2: selector for vcr video output mode vvcr2-0 vcrvout vcrc shutdown 000 hi-z hi-z encoder cvbs or y/c 1 001 encoder cvbs/y encv encoder chrominance encrc encoder cvbs or y/c 2 010 encoder cvbs/y ency encoder chrominance encc tv cvbs (default) 011 tv cvbs tvvin hi-z vcr 100 vcr cvbs/y vcrvin vcr r/c vcrrc (reserved) 101 - - (reserved) 110 - - (reserved) 111 - - table 12. vcr video output (see note) vrf0-1: selector for rf video output mode vrf1-0 rf cvbs encoder cvbs1 00 encoder cvbs1 encv encoder cvbs2 01 encoder cvbs2 encg (note: 22) vcr (default) 10 vcr vcrvin shutdown 11 hi-z table 13. rf video output (see note) note: 21: when input the video signal via encrc or vcrrc pin, set clamp1-0 bits respectively. note: 22 when vtv2-0=?001?, tvg=?1? and vrf1-0=?01?, rfv output is same as tvg (encoder g).
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 29 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h output enable cio tvfb vcrc vcrv tvb tvg tvr tvv r/w r/w default 0 0 0 0 0 0 0 0 each video outputs can be set to hi-z individually. tvv : tvvout output control tvr : tvrcout output control tvg : tvgout output control tvb : tvbout output control vcrv : vcrvout output control vcrc : vcrc output control tvfb : tvfb output control 0 : hi-z (default) 1 : active. when cio= ?1?, the vcrc pin is connected to gnd even if vcrc= ?0?. when cio= ?0?, the vcrc pin follows the setting of vcrc bit. cio: vcr chrominance i/o control 0 : active (output). 1 : connected to gnd cio vcrc state of vcrc pin 0 0 hi-z (default) 0 1 active 1 0 connected to gnd 1 1 connected to gnd table 14 vcrc output control
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 30 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h video volume 0 vclp1 vclp0 0 clamp1 clamp0 vvol1 vvol0 r/w r/w default 0 0 0 0 0 1 0 0 vvol1-0: rgb video gain control vvol1 vvol0 gain output level (typ. @input=0.7vpp) 0 0 +6db 1.4vpp (default) 0 1 +7.2db 1.6vpp 1 0 +8.2db 1.8vpp 1 1 +9.1db 2.0vpp table 15. rgb gain clamp1 : encoder r/chroma (encrc pin)input clamp control 0 : dc restore clamp active (for red signal. default) 1 : biased (for chroma signal.) clamp0 : vcr r/c (vcrc pin)input clamp control 0 : dc restore clamp active (for red signal) 1 : biased (for chroma signal. default.) vclp1-0 : dc restore source control vclp1 vclp0 sync source of dc restore 0 0 encv (default) 0 1 ency 1 0 vcrvin 1 1 (reserved) table 16. dc restore source control
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 31 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h s/f blanking sbio1 sbio0 sbv1 sbv0 sbt1 sbt0 fb1 fb0 r/w r/w default 0 0 0 0 0 0 0 0 fb1-0: tv fast blanking output control (for tvfb) fb1 fb0 tv fb output level 0 0 0v (default) 0 1 4v 1 0 same as vcr fb input (4v/0v) 1 1 (reserved) (note: minimum load is 150ohm) table 17. tv fast blanking output sbt1-0: tv slow blanking output control (for tvsb) sbt1-0 do not work correctly when vp<11.4v sbt1 sbt0 slow blanking output level 0 0 <2v (default) 0 1 5v<, <7v 1 0 (reserved) 1 1 10v< (note: minimum load is 10kohm) table 18. tv slow blanking output sbv1-0: vcr slow blanking output control (for vcrsb) sbv1-0 do not work correctly when vp<11.4v sbv1 sbv0 slow blanking output level 0 0 <2v (default) 0 1 5v<, <7v 1 0 (reserved) 1 1 10v< (note: minimum load is 10kohm) table 19. vcr slow blanking output sbio1-0: tv/vcr slow blanking i/o control sbio1-0 do not work correctly when vp<11.4v sbio1 sbio0 vcr slow blanking direction tv slow blanking direction 0 0 output (controlled by sbv1,0) output (controlled by sbt1,0) (default) 0 1 (reserved) (reserved) 1 0 input (stored in svcr1,0) output (controlled by sbt1,0) 1 1 input (stored in svcr1,0) output (same output as vcr sb) table 20. tv/vcr slow blanking output
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 32 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h sb/fb monitor 0 0 0 0 0 fvcr svcr1 svcr0 r/w read default 0 0 0 0 0 0 0 0 svcr1-0: vcr slow blanking status monitor those bits reflect the voltage at vcrsb pin for both input/output modes svcr1-0 do not work correctly when vp<11.4v svcr1 svcr0 vcrsb level 0 0 < 2v 0 1 4.5 to 7v 1 0 (reserved) 1 1 9.5< table 21. vcr slow blanking monitor fvcr: vcr fast blanking input level monitor this bit is enabled when tvfb bit = ?1?. fvcr vcrfb input level 0 <0.4v 1 1 v< table 22. vcr fast blanking monitor (typical threshold is 0.7v) changes to the 08h status can be monitored via the int pin. the int pin is the open drain output and goes ?l? for 2usec(typ.) when the status of 08h is changed. this pin should be connected to vd (typ. 5v) through 10kohm resister.
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 33 - system design tv scart y/cvbs r/c g b audio l audio r y/cvbs audio l audio r fast blank slow blank encoder y r/c g/cvbs b cvbs/y c vcr scart y/cvbs r/c g b audio l audio r y/cvbs audio l audio r fast blank slow blank audio mono cvbs rf mod mpeg decoder bick lrck sdata mclk micro processor sda sck pdn phono encv ency vcrvin tvvout encc encrc encgv encb sck sda pdn bick lrck sdata mclk vcrrc vcrc vcrg vcrb vcrinl vcrinr vcrvout vcroutl vcroutr vcrsb vcrfb tvfb tvoutl tvoutr tvvin tvrc tvg tvb tvinl tvinr tvsb rfv monoout interrupt int figure 17. typical connection diagram
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 34 - 1. grounding and power supply decoupling vd, vp, vvd1, vvd2, vss and vvss should be supplied from analog supply unit and be separated from system digital supply. decoupling capacitor, especially the 0.1 f ceramic capacitor for high frequency noise should be placed as near to vd (vp, vvd1, vvd2) as possible. 2. voltage reference each vcom is a signal ground of this chip. an electrolytic capacitor 10 f parallel with a 0.1 f ceramic capacitor attached to vcom pin eliminates the effects of high frequency noise. no load current may be drawn from vcom pin. all signals, especially clocks, should be kept away from vcom pins in order to avoid unwanted coupling into the ak4702. 3. analog audio outputs the analog outputs are also single-ended and centered on 5.6v(typ.). the output signal range is typically 2vrms (typ@vd=5v). the internal sw itched-capacitor filter and continuous-tim e filter attenuate the noi se generated by the delta-sigma modulator beyond the audio pass band. therefore, an y external filters are not required for typical application. the output voltage is a positive full scale for 7fffffh (@18bit) and a negative full scale for 800000h (@18bit). the ideal output is 5.6v(typ.) for 000000h (@18bit). the dc voltage on analog outputs are eliminated by ac coupling.
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 35 - 4. external circuit example analog audio input pin monoin tvinl/r vcrinl/ r 0.47f 300ohm (cable) analog audio output pin monoout tvoutl/r vcroutl/r 10f 300ohm total > 4.5kohm (cable) analog video input pin encv, ency, vcrvin, tvvin, encrc, encc, vcrrc, encg, vcrg, encb, vcrb 0.1f 75ohm (cable) 75ohm analog video output pin (except rfv pin) tvvout, tvrc tvg, tvr vcrvout, vcrc max 400pf 75ohm 75ohm max 15pf (cable) analog video output pin (rfv pin) the ak4702 does not have 75ohm driver. please use an external buffer if the input impedance of the rf modulator is less than 20kohm. rfv max 15pf buffer zin>20kohm rf modulator
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 36 - slow blanking pin tvsb vcrsb max 3nf (with 400ohm) 400ohm (max 500ohm) min: 10k ohm (cable) fast blanking input pin vcrfb 75ohm (cable) 75ohm fast blanking output pin tvfb 75ohm 75ohm (cable)
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 37 - package 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.22 0.08 48pin lqfp(unit:mm) 0.10 37 24 25 36 0.145 0.05 1.40 0.05 0.13 0.13 1.70max 0 10 0.10 m 0.5 0.2 0.5 ? package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 38 - marking AK4702EQ xxxxxxx 1 xxxxxxxx: date code identifier revision history date (yy/mm/dd) revision reason page contents 05/09/20 00 first edition
asahi kasei [AK4702EQ] ms0424-e-00 2005/09 - 39 - important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulati ons of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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